Re: emc on microway alpha pc?

[Jon Elson <jmelson-at-artsci.wustl.edu>]

"Terry L. Ridder" wrote:

> hello;
>
> this would be the test box for the bridgeport
> boss conversion. the bridgeports all have steppers.
> i am going to drive the bridgeport with two
> parallel ports. i need to order some of the least
> expensive isa cards.

You should know that the ISA bus is a HUGE bottleneck, and
getting worse as CPUs get faster.  You might do well to at
least have the stepper motors on a PCI parallel port.
The auxilliary stuff should be OK on the ISA.

> in talking with matt shaver concerning intel hardware
> limiting the ability of emc to drive steppers currently
> i was thinking of trying the alpha since the hardware
> is a little different and should not be the limiting
> factor. matt, sent me an excel spreadsheet which showed
> the limits under intel hardware.

Hmmm, I'd like to see that.

Once you get past the ISA bottleneck, the next concern is how
many interrupts/second you can hit the CPU with before it is totally
consumed servicing freqmod.  I don't know whether the Alpha
CPU does better or worse at this - it is somewhat dependent on
how smart the RT people were in taking advantage of the Alpha
CPU's features.  If they save the COMPLETE state of the entire
CPU every interrupt, it will be bad, because the CPU has a LOT
of registers!  If they are really sharp (and this depends a bit on how
much info is made available by the RT kernel mods) they could
save time by only saving those regs that would be changed by the
ISR.  There are also tricks that can be done using the PAL (Priveledged
Architecture Library) that allow you to effectively add instructions
(really macro-instructions) to the CPU, making context switches
faster.

Jon