Re: FPGA for PCI based servo control board

[John Sheahan <jrsheahan-at-optushome.com.au>]

On Sat, Apr 05, 2003 at 04:49:22PM -0500, John Kasunich wrote:
> 
> Joe User ain't gonna be re-compiling the FPGA to suit his
> mix of motors and I/O.  He has neither the tools or the
> know-how.

agree, but having the software select from a small number
of canned images is practical. Perhaps not necessary.

> 
> With ethernet, there are two possibilities.  One is to send
> a 256 byte packet from FPGA to PC, transferring the entire
>...
> makes it better, but your're still transferring far more data
> than is actually needed.

how come one scheme here always transmits max size data, and one 
transmits a delta?  All schemes could run either way.

And 100M ethernet today is probably the minimum it would be reasonable
to support.

> 
> I see the micro-fpga interface as a set of registers.  Not too
> complex at all.

which is the model used inside the pc. What did we gain with the
interface card exactly?

> 
> 1)  PCI - big FPGA, containing a PCI interface and the control
> hardware.  The control registers are mapped to a block of PCI
> I/O addresses.  PnP complicates things, but it really comes
> down to getting the base address to the EMC code somehow.

on a new SMD board inside the PC. Not complex, but 
hard to assemble. 
Whats the model for the connection between this card and the target?
some kind of wide, high-density connector? Thats what I was actually
trying to eliminate.   
The IO card is still required.

> 
> 2)  ISA - small FPGA, containing an ISA interface and the control
> hardware.  The control registers are mapped to a block of ISA I/O
> addresses.  The base address is set by jumpers, and entered into
> the EMC ini file.  Old-fashioned, but it works.
> 

what do we gain with this we do not have today?  Also the transaction
speed on the ISA interface is an issue for the real-time loops.


> 3)  EPP - small FPGA, containing an EPP interface and the control
> hardware.  The control registers are accessed sequentially through
> the EPP "bus".  The parallel port address (378h, etc.) is entered
> into the EMC ini file.
> 

yes. Again, seems to be pretty much what Jon has done well.


> 4)  Ethernet - big FPGA, containing an ethernet MAC and the
> control hardware.  The packet format is as I described above.
> The PC NIC ID (eth0, etc.) and the FPGA MAC address are
> entered into the EMC ini file.
> 

10 or 20 k gates I'd assume, but not a particularly high pin count.
probably plcc (hence socketable, hence buildable by most) 
On the same board as all the IO buffers, physically located close to
the machine.  My picture here is just a cheap longish cable.



> Most of the EMC code is the same for all 4 versions.  Versions
> 1 and 2 use the exact same code, once the base address is
> known.  Version 3 uses a simple interface layer that translates
> each access into one or two EPP cycles.  Version 4 uses a
> more complex interface layer that handles packets.
> 

moving the same sort of data to a register map in the NIC, then saying
go. not much more complex. Perhaps less cpu as it does not have to
bi bash out a slow interface.  (just how many cycles does a 1G pentium
waste sinning on an ISA read or write? 100's to thousands. ouch.