Re: FPGA for PCI based servo control board

["Dave Engvall" <dengvall-at-charter.net>]

As I understand it....1.0e-12 is about right for fiber.

:-)

D
----- Original Message -----
From: "John Sheahan" <jrsheahan-at-optushome.com.au>
To: "Multiple recipients of list" <emc-at-nist.gov>
Sent: Friday, April 04, 2003 4:53 PM
Subject: Re: FPGA for PCI based servo control board


>
> On Fri, Apr 04, 2003 at 07:19:08PM -0500, Jason Cox wrote:
>
> > the packet would contain all drive data , CRC and time-stamp. The time
> > stamp is there so that the controller would have a buffer (FIFO) to
> > allow for any slight variation in delivery times. there would also be a
> > return packet with all return controls ( ESTOP, time-stamp error ,....).
> > All that EMC needs is to send data to the controller as long as it
> > dosn't get an error. if it gets an error it can set a query bit in the
> > TX packet to find out the time-stamp of the error and backtrack to that
> > point in the data stream. All packets also will be compressed so that
> > the packet size shrinks with the number axis that are in operation.
> >
>
> shrinking packet size may not be all that useful. bandwidth here is cheap.
> I'm not sure what
> the right error behaviour is. Most machines cannot just stop and wait
> for the controller to catch up. Too much inertia.
> I'd tend to think no compression and absolute information may cope
> with errors better. When compressed, error propagation can be nasty.
>
> Just getting the error rate down to parts in 10^-12 would be my
> approach.  Thats an achievable goal. Flag CRC errors so the operator
> knows there is a transmission problem.
>
> > I am also working on a USB2.0 interface for this as the specs allow for
> > 480 Mbits/sec TX rate.
>
> have a look at the FT245BM for usb1.1 for a simple interface too.
> john
>