Re: emc on microway alpha pc?

[Jon Elson <jmelson-at-artsci.wustl.edu>]

"Terry L. Ridder" wrote:

> On Thu, 12 Oct 2000, Jon Elson wrote:
>
> "Terry L. Ridder" wrote:
>
> terrylr> hello;
> terrylr>
> terrylr> this would be the test box for the bridgeport
> terrylr> boss conversion. the bridgeports all have steppers.
> terrylr> i am going to drive the bridgeport with two
> terrylr> parallel ports. i need to order some of the least
> terrylr> expensive isa cards.
>
> jon>
> jon> You should know that the ISA bus is a HUGE bottleneck, and
> jon> getting worse as CPUs get faster.  You might do well to at
> jon> least have the stepper motors on a PCI parallel port.
> jon> The auxilliary stuff should be OK on the ISA.
> jon>
>
> now i have two people tell me two opposing points-of-view.
> one person is saying isa should be fine and the other is
> saying that isa parallel cards would be a bottleneck.
>
> a dual parallel port pci card must share an irq.
> to allow for individual irqs i would need to single
> parallel port pci cards.

But, the IRQ is NOT used by EMC for either the stepper pulse output
or the digital I/O for auxilliary control.

I don't know what sort of pulse resolution you are trying for.
I guess somewhere in the 50 uS granularity might be reasonable
(that's 20,000 interrupts/second from the timer).  Depending on
the RT overhead for the context switch and interrupt, it might
be possible to go faster.

Yes, I guess that a 1 uS cycle time for an ISA parallel port is pretty
small
compared to those rates.

I am working on a step pulse generator chip that would connect to the
parallel port, and drive 4 steppers, with pulse timing resolution down
to
100 nS.  Since this device is totally asynchronous to the CPU, the CPU
needs to have a way to count those pulses, so you need a quadrature
encoder counter chip, too.  That chip can either count stepper pulses or

use an actual shaft encoder on the motor.

Jon