Re: FPGA for PCI based servo control board

[John Sheahan <jrsheahan-at-optushome.com.au>]

On Sat, Apr 05, 2003 at 01:55:39AM -0500, Jon Elson wrote:
> >
> Well, why do you think the parallel port glitches?  I have run tests for 
> hours
> writing pseudo-random data into registers on my boards and the reading 
> it back,
> and checking for errors.  I haven't seen ANY errors, ever, on properly 
> running
> boards.

good to see you testing this way. too many engineers are too
trusting. Speaks well for the quality of your stuff.


Quite a few years ago I designed a rom simulator.  (ie a ram that
plugs in, connected up to the host pc via the parallel port) 
It proved popular in the small company I was at at the time, several dozen
were made. There were schmitt triggers on the clocks, waveforms were
good.

Running on perhaps 10 different PC's we found some were 100% reliable,
some would do one good load in about 3. Most were in the middle. 
It was always the PC+port that was suspect, based on swaps. 
Roughly a megabyte download.   Swapping the parallel port on machines
with ports on plugin boards affected it a bit. But it seems some
machines just missed port writes sometimes.  

Laplink and friends could occasionally flag background errors too.

perhaps things have improved. 
 
> 
> And, you should not have errors on a 2-node ethernet in a master/slave 
> operation.
> Really, the only errors are when more than one node tries to send at the 
> same
> time.

there are other phenomena beside collisions that can make errors on
transmisison links.   Well built links just have low error rates.


> 
> Jon
>