Re: New project...PCI based servo control board

[jmkasunich-at-ra.rockwell.com]

Jon Elson wrote:

> jmkasunich-at-ra.rockwell.com wrote:

>> First the output section.  This is based on the drawing I
>> posted earlier.
>>
>> Per axis:
>> Command register, 16 D Flipflops with clk ena (10 gates):  160
>> 26 bit Adder (16 gates per bit - is this reasonable?):     416
>> Accumulator, 26 D Flipflops (8 gates):                     208
>> Range selection mux (6 inputs):                             24
>> Output logic (the stuff to the right of the adder):         63
>>                                                        ------
>> Total gates per axis for output:                           871
>>
>> Now the encoder section.  Here I am assuming a 16 bit
>> up/down counter, a 16 bit register to capture the
>> count value, and a small state machine to convert
>> quadrature to up/down pulses
>>
>> Per axis:
>> Counter register, 16 D flipflops (8 gates):                128
>> Counter logic (12 gates per bit, is this reasonable?):     192
>> Capture register, 16 D flipflops with clk ena (10 gates):  160
>> Quadrature decoding state machine, 4 D FFs + logic:        100
>>                                                        ------
>> Total gates per axis for feedback:                         580
>>                                                        ------
>> Total gates per axis, output and feedback:                1451
>>

> This is way optimistic.  I'm using a 10000 gate FPGA for
> my 4 encoder counter board, and it is pretty full.

> I am using a 30,000 gate FPGA for my 4-axis stepper
> controller (encoder counters plus step rate generators)
> and it is pretty full, too.

Ouch!  Do you have any idea where I went wrong?  Using
your 4-encoder board for example, you have ~2500 gates
per encoder counter, and I got 580.  Are we comparing
apples to apples - 16 bit counter with capture register
and quadrature decoder?  I just don't understand how the
gate counts for the individual circuits can get so high.
Unless it's routing limited.  IIRC, when I was doing
Xilinx stuff years ago, routing was the limiting factor.


>> In another post, someone mentioned that the PCI interface
>> will run around 10K-20K gates.  It just blows my mind that
>> the bus interface might take more logic than actual control
>> hardware.

> Well, it takes some sophistication to keep the I/O flowing
> at full speed.  I suspect if you do slave only, no DMA and
> no auto configuration, it is MUCH less.  I've seen some MSI
> "TTL" PCI interfaces that were only about 5 74AHCxxx ICs.
> Mostly, an address comparator and 74AHC374's.

This is the first I've ever heard of a "simple" PCI interface.
Any links where I could look further, or should I just start
googling?

All we really need is the ability to read and write a few
dozen 8 or 16 bit registers.  DMA, bus mastering, and so on
are ridiculous for this application.

>> After I got the gate count, I hauled out the Digikey catalog
>> and looked at the choices.  I was looking for ~15K gates.
>>
>> Xilinx 4000 series - XC4013E-4PC160C - $102.00 <gasp, choke>
>> This is the most recent family I have any experience with.

> This is 10+ year old technology, stay away from it.
> The original Spartan is very similar, but much newer
> and cheaper.  5V.  My 30K gate XCS10TQ144 part in the
> Universal Stepper Controller is $30.  The XCS10PC84 in
> the encoder counter board is $12.

>> Xilinx 5200 series - XC5210-6PQ160C - $67.20 <still gasping>

>Antique.

>> That's all I saw in the Digikey catalog.  That catalog is
>> my standard for "readily available" parts.  I'm sure there
>> are other readily available parts, as well as dozens or
>> hundreds of harder to purchase choices.
>
>
> Maybe.  They are YEARS behind the times in what Xilinx
> parts they carry.

You obviously know where to buy small quantities of more
modern Xilinx parts.  What's the secret?

>> I think the interrupt latency under real time Linux is on
>> the order of 5-25uS.  Negligable at 1KHz, but starting to
>> be >> significant at at 20KHz where the total budget is 50uS.
>
> My PPMC and USC boards have update timers on them that
> allow them to be the source of the servo update rate.
> They also latch the encoder count and send the new
> velocity info to the DAC or rate generator.  That way,
> there is NO software-induced timing jitter!

I'm aware of that technique, that's why I assumed the
encoder counters would have capture registers.  A single
hardware signal would capture all encoder values at once.

> This is not used by the current version of EMC,

I didn't know that.

> but it could be used quite easily.  You just have to
> substitute the interrupt vector and let the RT scheduler
> know which interrupt you are supposed to be triggered by.

For ParPort interfaces I assume that is IRQ 7 or 5?

John Kasunich