RE: New project...PCI based servo control board

[Alex Kovacic <A.Kovacic-at-unsw.edu.au>]

At 02:42 PM 26/03/2003 -0500, you wrote:
>
>Hi John,
>
>Sounds like we are thinking along the same lines...  And yes, I'm certainly
>open to collaboration.  At this stage, I'm envisioning a single PCI card,
>with an architecture that is very tightly coupled to the primary CPU.
>That's why I've mostly considered the PCI bus, despite the complexity and
>cost drawbacks. It has low latency if properly implemented and is well
>supported by all OS's Most definitely FPGA based, because I'm sure we won't
>get it "right" the first time, at least with regard to feature set.
>Actually, I guess I'm thinking that if we can get the initial board design
>completed with just a basic set of functions implemented, it could "grow"
>over time to support more advanced features.  Initially I was thinking of
>primarily including the functionality of the Servo to Go ISA board, with
>stepper support being something for the future.  But as Ray says... Twist my
>arm...I agree we should try to get as many inputs as possible.  
>
>As you probably know, the PCI bus (and associated drivers) are fairly
>complex, at least if one wants to do a full implementation.  Even 32 bit,
>33MHz target only VHDL code for a FPGA instantiation is pretty pricey, but
>I'm working on some options.  If we can afford a large enough FPGA, there
>will be plenty of room for stepper pulse generators and GP I/O.  As you
>pointed out, there a large number of trade offs to be made with regard to
>how many features we try to include on single board, but that's the fun of a
>project like this.  I'm not very familiar with Jon Elson's designs, but I'll
>have a look at them.  I think it's fair to say I'm pretty firmly in the
>"single board" camp, as I really want a solution that is tightly coupled to
>the motherboard. But having said that.. I guess we could consider "daughter"
>cards....:)
>
>I'll try to have some sort of preliminary board spec to talk about at NAMES,
>capturing as much of everyone's input as I can.  I need to better understand
>what the programmers would like to see in way of interfaces.  I'm thinking
>that some sort of block I/O, reading or writing to multiple registers with
>one transaction would be preferred... But maybe single register is access
>fine.  Anyway LOTS to talk about, I hope we can hook up at NAMES.
>
>Best regards


High-Speed Buses: What is Beyond PCI?


I recall a while back discussions of a PCI bus type board…. I wonder what
has happened to that project..can someone enlighten us..The high price to
produce the board might be one reason the project has not progressed????…

The other reason why you should be carefull in developing a PCI bus
controller is that the next generation of PC will not have a PCI bus on the
motherboard.

Remember the EISA versus PCI versus VL-Bus wars? That battle ended with PCI
victorious. 

The current PCI bus is called the PCI-X standard. 
PCI-X is championed by three main players--Compaq, IBM, and HP.and , it
offers two new higher speeds, 100 MHz and 133 MHz., PCI-X will allow eight
33 MHz slots, four 66 MHz slots, two 100 MHz slots, or a single 133 MHz
slot per controller.

There are a plethora of players involved in replacing the PCI bus

1. InfiniBand, which stands for "infinite bandwidth", is one of the new
technologies that is not a direct PCI replacement (as is often assumed),
but is one of the most ambitious and complex of the new interconnects. With
key backing from Intel, Dell, Hitachi, Sun Microsystems, Hewlett-Packard,
IBM, and 3Com, InfiniBand is intended to be a specialized datacenter
server-to-server and server-to-storage interconnect, though it feels more
like a fully switched I/O networking architecture, than a traditional I/O bus.

2. A consortium called the Arapahoe Group, led by Intel, Compaq, HP and
Microsoft, has recently proposed a new standard called 3GIO (Third
Generation I/O) for now, which is meant to replace PCI as both an expansion
bus and chip-to-chip interconnect, and provide backward software
compatibility with its PCI ancestor. The PCI-SIG will take over the
management and promotion of 3GIO.

3. Two other high-performance, low latency buses, Motorola's RapidIO
(originally announced by Motorola at the Embedded Systems Conference in
Spring 2000) and AMD's HyperTransport, are aiming squarely at the
communications and embedded market. AMD is also targeting chip-to-chip
communications in the server and desktop market as well, and you may
already know HyperTransport is used in Nvidia's Nforce chipsets, and in the
Xbox as the interface between its NV2A and MCP chipset components (with an
Intel processor right nearby…).

As you would expect, the RapidIO Interconnect Architecture and Trade
Association includes communications heavy hitters like Motorola, Cisco,
Lucent, Nortel Networks, and Xilinx. The HyperTransport Consortium is a mix
of communications and system players, including AMD, Apple Computer, Cisco
Systems, nVidia, API Networks, PCM Sierra, and Sun Microsystems.

All these future interconnects and buses have a few things in common. They
use packet-based, point-to-point connections; in fact, InfiniBand
implements a full switch fabric. They provide bandwidth in multiples of
that offered by PCI. 

Having two competing bus structures--three, if PCI itself continues to
evolve--will put us back into the EISA/PCI/VL-Bus days of old.

So consider the above before you commit to a PCI design.

ps.. if you decide to proceed I will be glad to help...
Alex Kovacic
FISH Lab
CYTOGENETICS UNIT,
SEALS,Level 4, Campus Centre,
Prince Of Wales Hospital,
RANDWICK, NSW, 2031,
AUSTRALIA,
Tel: (61) (02) 9382 9168
Fax: (61) (02) 9382 9157
email1:A.Kovacic-at-unsw.edu.au
email2:kovacica-at-sesahs.nsw.gov.au
**********************************************************************
South Eastern Sydney Area Health Service

This email, and the files transmitted with it, are confidential and intended solely for the use of the individual or entity to whom they are addressed.

If you are not the intended recipient, you are not permitted to distribute or use this email or any of its attachments in any way.

We also request that you advise the sender of the incorrect addressing.

This note also confirms that this email message has been virus-scanned and although no computer viruses were detected, South Eastern Sydney Area Health Service accepts no liability for any consequential damage resulting from email containing any computer viruses.

**********************************************************************