Re: digital servo controller to offload the Parallel Port?

[Jon Elson <elson-at-pico-systems.com>]

Matt Shaver wrote:

>On Thursday 19 December 2002 12:24 pm, John wrote:
>
>  
>
>>IMHO, Jon's PPMC is the right direction as far as the interface to
>>the PC is concerned.  The EPP port gives fairly fast and simple
>>access to external hardware.
>>    
>>
>
>The only hitch (and Jon can confirm this) is that each "enhanced parallel 
>port" chip has it's own peculiarities when it comes to shifting to EPP mode. 
>I know Jon wrestled for a while with this and I don't know if he ever came up 
>with a universal method that works for all ports. Laptops in the distant 
>future may omit the parallel port, but they'll probably last longer than 
>desktop PCs since travellers want to be able to print wherever they go. For 
>desktops, the best bet is what JohnK suggested, use PCI parallel port boards 
>(Siig is nice).
>  
>
No, I still don't think I have a full handle on this.  I just had a 
customer with two slightly different
motherboards, which apparently had the SAME floppy/parport chip, but 
only one of them
would work with the univ step controller.  The only difference might be 
the BIOS setup for the
port mode, or some quirk in the motherboard.  I did find out some of the 
problems I had just
before the last NAMES show, and have made some slight changes so that 
these units work with
all the motherboards and floppy/parport chips I have access to.  The 
IEEE-1284 spec is QUITE clear
on the timing requirements, and I've YET to find a chip that actually 
meets the spec.  The data
lines are supposed to be set and stabilized before the clock line is 
strobed.  SMC chips do it
at the same time, UMC chips send the data AFTER the strobe line! 
 Amazing violation, no wonder
my boards didn't work at first!

>  
>
>>(DDS instead of divide-by-n)
>>    
>>
>
>Also, if you're looking for a nice DDS chip, check out the Analog devices 
>AD9833. It's serial loading, and you can bypass the sine rom and output a 
>plain square wave clock which saves you from having to "square up" the DDS 
>output. It's a preliminary datasheet now, but by the time any of us ever get 
>around to actually using one of these, it'll probably be obsolete ;) .
>  
>
This is massive overkill!  These chips aren't REAL expensive, but you'd 
only get one axis out of
it, and it doesn't handle step pulse width, or the direction signal at 
all.  You'd get a 50% duty cycle
on the step signal, which might be a problem with some drives.  Who 
needs 50 million steps/second,
anyway?  My $30 FPGA in the Universal stepper controller has 4 step rate 
generators, 4 encoder
counters, plus digital I/O, emergency stop, IEEE-1284 bus control, etc.

Jon