SV: wild I/O interface idea



I while back there was discutions about different interface cards. 
In the Swedich magazine Elektor (available in english to) there are an
article about using the PIC buss.

The card in the article are fairly simple to get, and seems like a perfect
card for experimanting with EMC. There are a lott of space on the card for
additional components like A/D's or whatever. 

The PCI-chip on the card are 16 bit in/out (but can of course be connected
to a 32/64 bit buss), it can only run on 33 MHz, and have a latency of less
than 90 ns. 

The card are more or less a PCI to ISA like interface. There are free
drivers to it as wel on the net. And it should be possible to use it with
Linux.

Could this be something?

Anders Blix

> -----Opprinnelig melding-----
> Fra:	Jim Register [SMTP:jtregister-at-att.net]
> Sendt:	28. april 2000 14:23
> Til:	Multiple recipients of list
> Emne:	Re: wild I/O interface idea
> 
> 
> At 02:53 PM 4/27/2000 -0400, Jon Elson wrote:
> >
> >Doug Fortune wrote:
> >
> >> Regarding the previous ISA/PCI/USB/ethernet etc
> >> conversations on how to get signals out to/from the real world
> >> in a timely manner for steppers and servos.
> >>
> >> The problem with ISA is that it is constrained to
> >> operate on an 8MHz cycle.  I believe the accesses to the
> >> parallel port and system timers (for RT-Linux) also
> >> must pass over this bus.
> >
> >No, the timer chip (assuming this is the system timer) is
> >on a motherboard chip set, and should be at near processor
> >speed.  If the parallel port is on the motherboard, the same is
> >true.  If the parallel port is a card plugged into the ISA, then it
> >will be restricted to ISA speed.  Since practically all Pentium
> >motherboards have at least one on-board parallel port, that
> >one should do fine for the real-time motion control.  A slow
> >parallel port could be used for the auxilliary controls.
> >
> >Note that the STG card is an 8-bit ISA card, and performs
> >quite well, with servo update times of 1 mS or less.
> 
> Minor correction:
> According to the STG manual, the DAC and ADC registers
> "must be accessed as full 16-bit words, not as bytes."  The
> encoder counters, each 24 bits wide, are arranged in pairs
> to allow 3 16-bit reads per pair, but may also be read a byte
> at a time, as I understand it.  Apparently STG is built to
> accomodate a much higher update rate than we are using.
> 
> General info for the curious:
> An 8-bit I/O read or write on the ISA bus requires 6 cycles
> of the 8.33 Mhz bus clock, or 720 ns; a 16-bit I/O operation
> requires 3 cycles, for 360 ns.  Performing 16-bit I/O via 
> 16-bit operations is not two, but four times as fast as 8-bit
> I/O, since two of the 8-bit cycles would be required.
> 
> For a four axis system (z, y, x and a rotary table) there would be
> 4 24-bit encoder counters to read, and 4 16-bit (13 bit actual)
> D/A registers to write, per update cycle.  Total I/O cycle time
> with 16-bit transfers would be 3.6 us, using 8-bit transfers
> would require 14.4 us.
> 
> None of this appears to be relevant to EMC;  with servos,
> there's a lot of I/O, but it's only done every millisecond.
> With steppers, I/O happens at the step rate, but one write
> can step all four axis at once, assuming they are all on
> the same parallel port.  I just did the math to see for myself.
> 
> Jim



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